RISC-V Instruction-Set Cheatsheet

Overview of the RV32I base instruction-set of RISC-V processors

A number of people have tried to make sheets giving an overview of the RISC-V instruction-set, so here is my variant. I have tried to find a balance between being useful and easy to read. That means some things I have excluded from this overview.

RISC-V Cheatsheet

I have also added this sheet to help compare RISC-V instructions with AVR. The comparison is quite imperfect as many instructions don’t have a good translation and I am leaving out a number of RISC-V and AVR instructions.

RISC-V compared to AVR

To get a full overview of AVR instructions you should look at: AVR instruction set.

Some obvious differences between RISC-V and AVR is that AVR instructions are defined to be 16-bit wide while RISC-V instructions are 32-bit.

What muddies the water a bit is that there are a few AVR instructions which are not 16-bit such as CALL, LDS, STS and JMP, while on RISC-V you can use compressed instructions if you have the C extension added. Compressed RISC-V instructions are 16-bit and look a lot like AVR instructions in terms of number of operands and bit sizes of immediate values.

I have collected all the cheat sheets into one larger document which also contains a comparison of the compressed RISC-V instructions with AVR.

Multi-page RISC-V vs AVR comparison

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